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| SEMICONDUCTOR TECHNICAL DATA Order this document by MRF136Y/D The RF MOSFET Line RF Power Field-Effect Transistor N-Channel Enhancement-Mode MOSFET Designed for wideband large-signal amplifier and oscillator applications up to 400 MHz range, in either single ended or push-pull configuration. * Guaranteed 28 Volt, 150 MHz Performance Output Power = 30 Watts Broadband Gain = 14 dB (Typ) Efficiency = 54% (Typical) * Small-Signal and Large-Signal Characterization * 100% Tested For Load Mismatch At All Phase Angles With 30:1 VSWR * Space Saving Package For Push-Pull Circuit Applications * Excellent Thermal Stability, Ideally Suited For Class A Operation * Facilitates Manual Gain Control, ALC and Modulation Techniques MRF136Y 30 W, to 400 MHz N-CHANNEL MOS BROADBAND RF POWER FET D G G S (FLANGE) CASE 319B-02, STYLE 1 D MAXIMUM RATINGS Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage Drain Current -- Continuous Total Device Dissipation @ TC = 25C Derate above 25C Storage Temperature Range Operating Junction Temperature Symbol VDSS VDGR VGS ID PD Tstg TJ Value Val e 65 65 40 5.0 100 0.571 -65 to +150 200 Unit Vdc Vdc Vdc Adc Watts W/C C C THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction to Case Symbol RJC Max 1.75 Unit C/W Handling and Packaging -- MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed. REV 0 1 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS (1) Drain-Source Breakdown Voltage (VGS = 0, ID = 5.0 mA) Zero-Gate Voltage Drain Current (VDS = 28 V, VGS = 0) Gate-Source Leakage Current (VGS = 40 V, VDS = 0) V(BR)DSS IDSS IGSS 65 -- -- -- -- -- -- 2.0 1.0 Vdc mAdc Adc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = 10 V, ID = 25 mA) Forward Transconductance (VDS = 10 V, ID = 250 mA) VGS(th) gfs 1.0 250 3.0 400 6.0 -- Vdc mmhos DYNAMIC CHARACTERISTICS (1) Input Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1.0 MHz) Ciss Coss Crss -- -- -- 24 27 5.5 -- -- -- pF pF pF FUNCTIONAL CHARACTERISTICS (2) Common Source Power Gain (Figure 1) (VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA) Drain Efficiency (Figure 1) (VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA) Electrical Ruggedness (Figure 1) (VDD = 28 Vdc, Pout = 30 W, f = 150 MHz, IDQ = 100 mA, VSWR 30:1 at all Phase Angles) NOTES: 1. Each side measured separately. 2. Measured in push-pull configuration. Gps No Degradation in Output Power 12 50 14 54 -- -- dB % REV 0 2 R4 BIAS ADJUST D1 C11 RFC1 C2 R2 C3 R5 R6 C5 C6 RFC2 C8 C7 VDD = +28 V R1 RF INPUT C1 A G B G R3 DUT D C9 C4 D T2 S T1 RF OUTPUT C10 C1 -- 5.0 pF C2, C3, C4, C6, C7, C9, C11 -- 0.1 F Ceramic C5, C8 -- 680 pF Feedthru C10 -- 15 pF D1 -- 1N4740 Motorola Zener RFC1 -- 17 Turns, #24 AWG Wound on R5 RFC2 -- Ferroxcube VK-200-19/4B or Equivalent R1 -- 10 k, 1/4 W R2, R3 -- 560 , 1/2 W R4 -- 10 Turns, 10 k R5 -- 56 k, 1 W R6 -- 1.6 k, 1/4 W T1 -- Primary Winding -- 3 Turns #28 Enameled Wire. T1 -- Secondary Winding -- 2 Turns #28 Enameled Wire. T1 -- Both windings wound through a Fair/Rite Balun 65 core. T1 -- Part #2865002402. T2 -- 1:1 Transformer Wound Bifilar -- 2 Turns Twisted Pair T1 -- #24 Enameled Wire through a Indiana General Balun Q1 T1 -- core. Part #18006-1-Q1. Primary winding center tapped. Board Material -- 0.062 G10, 1 oz. Cu Clad, Double Sided Figure 1. 30-150 MHz Test Circuit 20 Pout , OUTPUT POWER (WATTS) 18 16 14 12 10 8 6 4 2 0 0 200 VDD = 28 V IDQ = 25 mA 400 600 800 Pin, INPUT POWER (MILLWATTS) f = 100 MHz 150 MHz 200 MHz 10 Pout , OUTPUT POWER (WATTS) 9 8 7 6 5 4 3 2 1 1000 0 0 200 VDD = 13.5 V IDQ = 25 mA 200 MHz f = 100 MHz 150 MHz 400 600 800 Pin, INPUT POWER (MILLWATTS) 1000 Figure 2. Output Power versus Input Power Figure 3. Output Power versus Input Power REV 0 3 20 Pout , OUTPUT POWER (WATTS) 18 16 14 12 10 8 6 4 2 0 0 1 2 Pin, INPUT POWER (WATTS) 3 4 VDD = 13.5 V f = 400 MHz IDQ = 25 mA VDD = 28 V 24 Pout , OUTPUT POWER (WATTS) 21 18 15 12 9 6 3 0 12 14 IDQ = 25 mA f = 100 MHz 18 22 16 20 24 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 Pin = 600 mW 400 mW 200 mW Figure 4. Output Power versus Input Power Figure 5. Output Power versus Supply Voltage 24 Pout , OUTPUT POWER (WATTS) 21 18 15 12 9 6 3 0 12 14 16 Pin = 900 mW 24 Pout , OUTPUT POWER (WATTS) 21 18 15 12 9 6 3 Pin = 1 W 600 mW 0.7 W 0.4 W IDQ = 25 mA f = 200 MHz 14 16 18 20 22 24 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 300 mW IDQ = 25 mA f = 150 MHz 18 22 20 24 VDD, SUPPLY VOLTAGE (VOLTS) 26 28 0 12 Figure 6. Output Power versus Supply Voltage Figure 7. Output Power versus Supply Voltage VGS, GATE SOURCE VOLTAGE (NORMALIZED) 2 I D, DRAIN CURRENT (MILLAMPS) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 VDS, GATE-SOURCE VOLTAGE (VOLTS) 6 7 VDS = 10 V TYPICAL DEVICE SHOWN, VGS(th) = 3 V 1.04 1.03 1.02 1.01 1 0.99 0.98 0.97 0.96 0.95 0.94 -25 0 VDS = 28 V ID = 750 mA 500 mA 250 mA 25 mA 25 75 125 50 100 TC, CASE TEMPERATURE (C) 150 175 Figure 8. Drain Current versus Gate Voltage (Transfer Characteristics)* Figure 9. Gate-Source Voltage versus Case Temperature* REV 0 4 100 180 C, CAPACITANCE (pF) 60 VGS = 0 V f = 1 MHz Coss Ciss Crss 10 5 3 2 1 TC = 25C 40 20 0 I D, DRAIN CURRENT (AMPS) 0.3 0.2 0 4 8 12 16 20 24 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 28 0.1 1 2 20 30 50 70 3 5 10 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 100 Figure 10. Capacitance versus Drain-Source Voltage Figure 11. DC Safe Operating Area TYPICAL PERFORMANCE IN BROADBAND TEST CIRCUIT (Refer to Figure 1) 40 Pout , OUTPUT POWER (WATTS) 35 POWER GAIN (dB) 30 25 20 15 10 5 0 0 0.5 1 1.5 Pin, INPUT POWER (WATTS) 2 2.5 f = 150 MHz 30 MHz VDD = 28 V IDQ = 100 mA 16 14 12 10 8 6 4 2 0 0 20 40 60 100 80 f, FREQUENCY (MHz) 120 140 160 VDD = 28 V IDQ = 100 mA Pout = 30 W Figure 12. Output Power versus Input Power Figure 13. Power Gain versus Frequency 100 Pout , OUTPUT POWER (WATTS) 90 80 , EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 20 40 60 80 100 f, FREQUENCY (MHz) 120 140 160 VDD = 28 V IDQ = 100 mA Pout = 30 W 30 25 20 15 10 5 0 -6 -4 -2 0 2 VGS, GATE-SOURCE VOLTAGE (VOLTS) 4 6 VDD = 28 V IDQ = 100 mA Pin = CONSTANT TYPICAL DEVICE SHOWN, VGS(th) = 3 V f = 150 MHz 30 MHz Figure 14. Drain Efficiency versus Frequency Figure 15. Output Power versus Gate Voltage REV 0 5 TYPICAL 400 MHz PERFORMANCE 40 Pout , OUTPUT POWER (WATTS) Pout , OUTPUT POWER (WATTS) 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 Pin, INPUT POWER (WATTS) VDD = 28 V IDQ = 100 mA f = 400 MHz 3 3.5 40 35 30 25 20 15 10 5 0 -4 -3 -1 1 -2 0 2 VGS, GATE-SOURCE VOLTAGE (VOLTS) 3 4 f = 400 MHz VDD = 28 V IDQ = 100 mA Pin = CONSTANT TYPICAL DEVICE SHOWN, VGS(th) = 3 V Figure 16. Output Power versus Input Power Figure 17. Output Power versus Gate Voltage 400 225 Zin & ZOL* are given from drain-to-drain and gate-to-gate respectively. 150 Zin 225 400 f MHz ZOL* 150 100 30 50 100 150 225 400 VDD = 28 V, IDQ = 100 mA, Pout = 30 W Zin{ Ohms 59.3 - j24 48 - j33.5 20.5 - j34.2 4.77 - j25.4 3 - j9.5 2.34 - j3.31 ZOL* Ohms 40.1 - j8.52 37 - j11.9 29 - j16.5 20.6 - j19 13 - j16.7 10.2 - j14.3 100 50 f = 30 MHz 50 f = 30 MHz Feedback loops: 560 ohms in series with 0.1 F Drain to gate, each side of push-pull FET ZOL* = Conjugate of the optimum load imped ance into which the device operates at a given output power, voltage and frequency. Figure 18. Input and Output Impedance REV 0 6 +j50 +j25 +j100 +j150 +j10 f = 800 MHz 10 +90 +120 +60 f = 800 MHz S12 0.14 0.10 0.06 0.02 +150 +30 600 400 70 +j250 +j500 25 50 100 150 250 500 0 400 180 -j500 0.18 0.16 0.12 0.08 0.04 0 150 -j10 70 S11 -j250 -j150 -150 -60 -90 -30 -j25 -j50 -j100 -120 Figure 19. S11, Input Reflection Coefficient versus Frequency VDS = 28 V ID = 0.5 A Figure 20. S12, Reverse Transmission Coefficient versus Frequency VDS = 28 V ID = 0.5 A +90 +120 70 100 +150 S21 150 400 f = 800 MHz +30 +j10 10 25 +j50 +60 +j25 +j100 +j150 +j250 +j500 0 f = 800 MHz 150 400 70 -j10 S22 -j25 -j50 0 50 100 150 250 500 180 8 6 4 2 -j500 -j250 -j150 -j100 -150 -60 -90 -30 -120 Figure 21. S21, Forward Transmission Coefficient versus Frequency VDS = 28 V ID = 0.5 A Figure 22. S22, Output Reflection Coefficient versus Frequency VDS = 28 V ID = 0.5 A REV 0 7 DESIGN CONSIDERATIONS The MRF136Y is an RF power N-Channel enhancement mode field-effect transistor (FET) designed especially for HF and VHF power amplifier applications. M/A-COM RF MOS FETs feature planar design for optimum manufacturability. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. The major advantages of RF power FETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal, thus facilitating manual gain control, ALC and modulation. DC BIAS The MRF136Y is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied without gate bias. A positive gate voltage causes drain current to flow (see Figure 8). RF power FETs require forward bias for optimum gain and power output. A Class AB condition with quiescent drain current (IDQ) in the 25-100 mA range is sufficient for many applications. For special requirements such as linear amplification, IDQ may have to be adjusted to optimize the critical parameters. The MOS gate is a dc open circuit. Since the gate bias circuit does not have to deliver any current to the FET, a simple resistive divider arrangement may sometimes suffice for this function. Special applications may require more elaborate gate bias systems. GAIN CONTROL Power output of the MRF136Y may be controlled from rated values down to the milliwatt region (>20 dB reduction in power output with constant input power) by varying the dc gate voltage. This feature, not available in bipolar RF power devices, facilitates the incorporation of manual gain control, AGC/ALC and modulation schemes into system designs. A full range of power output control may require dc gate voltage excursions into the negative region. AMPLIFIER DESIGN Impedance matching networks similar to those used with bipolar transistors are suitable for the MRF136Y. See M/A-COM Application Note AN721, Impedance Matching Networks Applied to RF Power Transistors. Large signal impedance parameters are provided. Large signal impedances should be used for network designs wherever possible. While the s parameters will not produce an exact design solution for high power operation, they do yield a good first approximation. This is particularly useful at frequencies outside those presented in the large signal impedance plots. RF power FETs are triode devices and are therefore not unilateral. This, coupled with the very high gain, yields a device capable of self oscillation. Stability may be achieved using techniques such as drain loading, input shunt resistive loading, or feedback. S parameter stability analysis can provide useful information in the selection of loading and/or feedback to insure stable operation. The MRF136Y was characterized with a resistive feedback loop around each of its two active devices. For further discussion of RF amplifier stability and the use of two port parameters in RF amplifier design, see M/A-COM Application Note AN215A. LOW NOISE OPERATION Input resistive loading will degrade noise performance, and noise figure may vary significantly with gate driving impedance. A low loss input matching network with its gate impedance optimized for lowest noise is recommended. REV 0 8 PACKAGE DIMENSIONS IDENTIFICATION NOTCH -A- L 4 3 Q 2 PL 0.15 (0.006) -N- M TA M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. M DIM A B C D E F H J K L N Q INCHES MIN MAX 0.965 0.985 0.355 0.375 0.230 0.260 0.055 0.065 0.102 0.114 0.055 0.065 0.160 0.170 0.004 0.006 0.120 0.140 0.725 BSC 0.225 0.241 0.125 0.135 MILLIMETERS MIN MAX 24.51 25.02 9.02 9.52 5.84 6.60 1.40 1.65 2.59 2.90 1.40 1.65 4.06 4.31 0.10 0.15 3.05 3.55 18.42 BSC 5.72 6.12 3.18 3.42 K D 1 2 F 4 PL 0.38 (0.015) B J H M TA M M N M M 0.38 (0.015) C E TA N M -T- SEATING PLANE STYLE 1: PIN 1. 2. 3. 4. GATE (INPUT) GATE (INPUT) DRAIN (OUTPUT) DRAIN (OUTPUT) SOURCE IS FLANGE CASE 319B-02 ISSUE C Specifications subject to change without notice. n North America: Tel. (800) 366-2266, Fax (800) 618-8883 n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298 n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020 Visit www.macom.com for additional data sheets and product information. REV 0 9 |
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